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SN74LS164 Serial-In Parallel-Out Shift Register
The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products.
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* * * * * *
Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts
14
LOW POWER SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA
1
PLASTIC N SUFFIX CASE 646
14 1
SOIC D SUFFIX CASE 751A
ORDERING INFORMATION
Device SN74LS164N SN74LS164D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS164/D
SN74LS164
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR 9 CP 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND
LOADING (Note a) PIN NAMES A, B CP MR Q0 - Q7 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC SYMBOL
1 2 8
A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 34 5 6 10 11 12 13
VCC = PIN 14 GND = PIN 7
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SN74LS164
LOGIC DIAGRAM
1 2
A D B CD CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0
3
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
8
9
Q1
4
Q2
5
Q3
6
Q4
10
Q5
11
Q6
12
Q7
13
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A*B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.
MODE SELECT -- TRUTH TABLE
OPERATING MODE Reset (Clear) Shift INPUTS MR L H H H H A X I I h h B X I h I h OUTPUTS Q0 L L L L H Q1-Q7 L-L q0 - q6 q0 - q6 q0 - q6 q0 - q6
L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don't Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition.
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SN74LS164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 -100 27 0.5 20 V A mA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIH or VIL per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C)
Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay MR to Output Q Propagation Delay Clock to Output Q Min 25 Typ 36 24 17 21 36 27 32 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions
AC SETUP REQUIREMENTS (TA = 25C)
Limits Symbol tW ts th trec Parameter CP, MR Pulse Width Data Setup Time Data Hold Time MR to Clock Recovery Time Min 20 15 5.0 20 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions
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SN74LS164
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
I/f max
MR 1.3 V
1.3 V CP
tW 1.3 V tPHL
1.3 V tW
1.3 V trec 1.3 V
tPLH 1.3 V CP tPHL
Q
1.3 V CONDITIONS: MR = H
Q
1.3 V
Figure 1. Clock to Output Delays and Clock Pulse Width
Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time
1/fmax tW CP 1.3 V ts(H) D * 1.3 V 1.3 V 1.3 V ts(L) 1.3 V 1.3 V
th(H) 1.3 V
th(L) 1.3 V
Q
1.3 V
1.3 V
Figure 3. Data Setup and Hold Times
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SN74LS164
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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SN74LS164
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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SN74LS164
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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SN74LS164/D

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